Intel 430NX (PCIset NX Neptune)

Chipset parts: Intel 82433NX (LBX) Intel 82434NX (PCMC) Intel 82378ZB (SIO)

Description
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Release date:  1994-03    [Encyclopedia link]   [see all boards with this chipset]

Overview

The 82430NX PCIsets provide the Host/PCI bridge, cache/main memory controller, and an I/O subsystem core (either PCI/EISA or PCI/ISA bridge) for the next generation of high-performance personal computers based on the Pentium processor. System designers can take advantage of the power of the PCI Local bus for the local I/O while maintaining access to the large base of EISA and ISA expansion cards, and corresponding software applications. Extensive buffering and buffer management within the bridges ensures maximum efficiency in all three bus environments (Host CPU, PCI, and EISA/ISA Buses).

The 82430NX PCIset consists of the 82434NX PCI/Cache Memory Controller (PCMC) and the 82433NX Local Bus Accelerator (LBX) components, plus, either a PCI/ISA bridge or a PCI/EISA bridge. For an ISA-based system, the 82430NX PCIset includes the 82378ZB System I/O (SIO) component as the PCI/ISA bridge. For the DP ISA based system, the 82430NX PCIset includes the 82379AB. For UP or DP EISA-based systems, the 82430NX PCIset includes the 82375EB/SB PCI/EISABridge (PCEB) and the 82374EB/SB EISA System Component (ESC).

Features:

  • Supports the Pentium Processor at iCOMP Index 735\90 MHz, Pentium Processor iCOMP Index 815\100 MHz, and Pentium Processor iCOMP Index 610\75 MHz
  • Supports Uni-Processor (UP) or Duel-Processor (DP) Configurations
  • Interfaces the Host and Standard Buses to the PCI Local Bus
    • Up to 132 MBytes/Sec Transfer Rate
    • Full Concurrency Between CPU Host Bus and PCI Bus Transactions
  • Integrated Cache Controller Provided for Optional Second Level Cache
    • 256 KByte or 512 KByte Cache
    • Write-Back Policy (82430NX)
    • Standard or Burst SRAM
  • Integrated Tag RAM for Cost Savings on Second Level Cache
  • Supports the Pipelined Address Mode of the Pentium Processor for Higher Performance
  • Provides a 64-Bit Interface to DRAM Memory
    • From 2 MBytes to 512 MBytes of Main Memory
    • 70 ns and 60 ns DRAMs Supported
  • Optional ISA or EISA Standard Bus Interface
    • Single Component ISA Controller
    • Two Component EISA Bus Interface
    • Minimal External Logic Required
  • Supports Burst Read and Writes of Memory from the CPU and PCI Buses
  • Five Integrated Write Posting and Read Prefetch Buffers Increase CPU and PCI Performance
  • Host CPU Writes to PCI Converted to Zero Walt-State PCI Bursts with Optional TROY # Connection
  • Integrated Low Skew Host Bus Clock Driver for Cost and Board Space Savings
  • PCIset Operates Synchronous to the CPU and PCI Clocks
  • Byte Parity Support for the Host and Main Memory Buses
    • Optional Parity on the Second Level Cache

82433NX (LBX) Overview

Two 82433NX Local Bus Accelerator (LBX) components provide a 64-bit data path between the host CPU/Cache and main memory, a 32-bit data path between the host CPU bus and PCI Local Bus, and a 32-bit data path between the PCI Local Bus and main memory. The dual-port architecture allows concurrent operations on the host and PCI Buses. The LBXs incorporate three write posting buffers and two read prefetch buffers to increase CPU and PCI performance. The LBX supports byte parity for the host and main memory buses. The 82433NX is intended to be used with the 82434NX PCI/Cache/Memory Controller (PCMC). During bus operations between the host, main memory and PCI, the PCMC commands the LBXs to perform functions such as latching address and data, merging data, and enabling output buffers. Together, these three components form a "Host Bridge" that provides a full function dual-port data path interface, linking the host CPU and PCI bus to main memory.

82433NX Features

  • Supports the Full 64-bit Pentium Processor Data Bus at Frequencies up to 66 MHz (82433LX and 82433NX)
  • Drives 3.3V Signal Levels on the CPU Data and Address Buses (82433NX)
  • Provides a 64-Bit Interface to DRAM and a 32-Bit Interface to PCI
  • Five Integrated Write Posting and Read Prefetch Buffers Increase CPU and PCI Performance
    • CPU-to-Memory Posted Write Buffer 4 Qwords Deep
    • PCI-to-Memory Posted Write Buffer Two Buffers, 4 Dwords Each
    • PCI-to-Memory Read Prefetch Buffer 4 Qwords Deep
    • CPU-to-PCI Posted Write Buffer 4 Dwords Deep
    • CPU-to-PCI Read Prefetch Buffer 4 Dwords Deep
  • CPU-to-Memory and CPU-to-PCI Write Posting Buffers Accelerate Write Performance
  • Dual-Port Architecture Allows Concurrent Operations on the Host and PCI Buses
  • Operates Synchronously to the CPU and PCI Clocks
  • Supports Burst Read and Writes of Memory from the Host and PCI Buses
  • Sequential CPU Writes to PCI Converted to Zero Wait-State PCI Bursts with Optional TRDY Connection
  • Byte Parity Support for the Host and Memory Buses
    • Optional Parity Generation for Host to Memory Transfers
    • Optional Parity Checking for the Secondary Cache
    • Parity Checking for Host and PCI Memory Reads
    • Parity Generation for PCI to Memory Writes

82434NX (PCMC) Overview

The 82434NX PCI, Cache, Memory Controllers (PCMC) integrate the cache and main memory DRAM control functions and provide bus control for transfers between the CPU, cache, main memory, and the PCI Local Bus. The cache controller supports write-back cache policy and cache sizes of 256-KBytes and 512-KBytes. The cache memory can be implemented with either standard or burst SRAMs. The PCMC cache controller integrates a high-performance Tag RAM to reduce system BOM cost.

82434NX Features:

  • Supports Uni-Processor (UP) or Duel-Processor (DP) Configurations
  • Interfaces the Host and Standard Buses to the 32bit PCI Local Bus
    • Up to 133 MB/s standard PCI Transfer Rate
    • Full Concurrency Between CPU Host Bus and PCI Bus Transactions
  • Integrated Cache Controller Provided for Optional Second Level Cache
    • 256 KByte or 512 KByte Cache
    • Write-Back Policy (82430NX)
    • Standard Asynchronous or Pipelined Burst SRAM
    • Support 0 wait state SRAM control
  • Integrated 4096 entry TAG ram allows for full 512MB address range cache lookup
  • Supports the Pipelined Address Mode of the Pentium Processor for Higher Performance
  • Provides a 64-Bit Interface to FPM DRAM Memory
    • 12 Address lines allow from 2 MBytes to 512 MBytes of Main Memory in 4 or 8 slot configuraitons
    • Support high capacity 64 and 128MB FPM modules
    • 70 ns and 60 ns DRAMs Supported
    • Support interleaved memory access
  • Optional ISA or EISA Standard Bus Interface
    • Single Component ISA Controller
    • Two Component EISA Bus Interface
    • Minimal External Logic Required
  • Supports Burst Read and Writes of Memory from the CPU and PCI Buses
  • Five Integrated Write Posting and Read Prefetch Buffers Increase CPU and PCI Performance
  • Host CPU Writes to PCI Converted to Zero Walt-State PCI Bursts with Optional TROY # Connection
  • Integrated Low Skew Host Bus Clock Driver for Cost and Board Space Savings
  • PCIset Operates Synchronous to the CPU and PCI Clocks
  • Byte Parity Support for the Host and Main Memory Buses
    • Optional Parity on the Second Level Cache
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