Description:

82378ZB (SIO) Overview

The 82378ZB System I/O (SIO) component provides the bridge between the PCI bus and the ISA expansion bus. The 82378ZB also integrates many of the common I/O functions found in ISA based PC systems. The 82378ZB incorporates the logic for a PCI interface (master and slave), ISA interface (master and slave), enhanced seven channel DMA controller that supports data buffers to isolate the PCI bus from the ISA bus and to enhance performance, PCI and ISA arbitration, 14 level interrupt controller, a 16-bit BIOS timer, three programmable timer/counters, and Non-Maskable Interrupt (NMI) Control Logic. The 82378ZB also provides decode for peripheral devices such as the Flash BIOS, Real Time Clock, Keyboard/Mouse Controller, Floppy Controller, two Serial Ports, one Parallel Port, and IDE Hard Disk Drive.

The 82378ZB supports several Advanced Power Management features such as SMI# Interrupt. The 82378ZB also supports a total of 6 PCI Masters, and can support up to 4 PCI Interrupts.

82378ZB Features:

• Provides the Bridge between the PCI Bus and ISA Bus
• 100% PCI and ISA Compatible
  • PCI and ISA Master/Slave Interface
  • Directly Drives 10 PCI Loads and 6 ISA Slots
  • Supports PCI at 25 MHz and 33 MHz
  • Supports ISA from 6 MHz to 8.33 MHz
• Enhanced DMA Functions
  • Scatter/Gather (S/G)
  • Fast DMA Type A, B, and F
  • Compatible DMA Transfers
  • 32-Bit Addressability
  • Seven Independently Programmable Channels
  • Functionality of Two 82C37A DMA Controllers
• Integrated Data Buffers to Improve Performance
  • 8-Byte DMA/ISA Master Line Buffer
  • 32-Bit Posted Memory Write Buffer to ISA
• Integrated 16-Bit BIOS Timer
• Non-Maskable Interrupts (NMI)
  • PCI System Errors
  • ISA Parity Errors
• Four Dedicated PCI Interrupts
  • Level Sensitive
  • Can be Mapped to Any Unused Interrupt
• Arbitration for ISA Devices
  • ISA Masters
  • DMA and Refresh
• Arbitration for PCI Devices
  • Six PCI Masters Are Supported
  • Fixed, Rotating, or a Combination of the Two
• Utility Bus (X-Bus) Peripheral Support
  • Provides Chip Select Decode
  • Controls Lower X-Bus Data Byte Transceiver
• Integrates the Functionality of One 82C54 Timer
  • System Timer
  • Refresh Request
  • Speaker Tone Output
• Integrates the Functionality of Two 82C59 Interrupt Controllers
  • 14 Interrupts Supported
  • Edge/Level Selectable Interrupts; Each Interrupt Individually Programmable
• Complete Support for SL Enhanced Intel486 CPU's
  • SMI# Generation Based on System Hardware Events
  • STPCLK# Generation to Power Down the CPU