Description:

82434NX (PCMC) Overview

The 82434NX PCI, Cache, Memory Controllers (PCMC) integrate the cache and main memory DRAM control functions and provide bus control for transfers between the CPU, cache, main memory, and the PCI Local Bus. The cache controller supports write-back cache policy and cache sizes of 256-KBytes and 512-KBytes. The cache memory can be implemented with either standard or burst SRAMs. The PCMC cache controller integrates a high-performance Tag RAM to reduce system BOM cost.

82434NX Features:

• Supports Uni-Processor (UP) or Dual-Processor (DP) Configurations
• Interfaces the Host and Standard Buses to the 32bit PCI Local Bus
  • Up to 133 MB/s standard PCI Transfer Rate
  • Full Concurrency Between CPU Host Bus and PCI Bus Transactions
• Integrated Cache Controller Provided for Optional Second Level Cache
  • 256 KByte or 512 KByte Cache
  • Write-Back Policy (82430NX)
  • Standard Asynchronous or Pipelined Burst SRAM
  • Support 0 wait state SRAM control
• Integrated 4096 entry TAG ram allows for full 512MB address range cache lookup
• Supports the Pipelined Address Mode of the Pentium Processor for Higher Performance
• Provides a 64-Bit Interface to FPM DRAM Memory
  • 12 Address lines allow from 2 MBytes to 512 MBytes of Main Memory in 4 or 8 slot configuraitons
  • Support high capacity 64 and 128MB FPM modules
  • 70 ns and 60 ns DRAMs Supported
  • Support interleaved memory access
• Optional ISA or EISA Standard Bus Interface
  • Single Component ISA Controller
  • Two Component EISA Bus Interface
  • Minimal External Logic Required
• Supports Burst Read and Writes of Memory from the CPU and PCI Buses
• Five Integrated Write Posting and Read Prefetch Buffers Increase CPU and PCI Performance
• Host CPU Writes to PCI Converted to Zero Walt-State PCI Bursts with Optional TROY # Connection
• Integrated Low Skew Host Bus Clock Driver for Cost and Board Space Savings
• PCIset Operates Synchronous to the CPU and PCI Clocks
• Byte Parity Support for the Host and Main Memory Buses
  • Optional Parity on the Second Level Cache