Description:

82358DT EISA Bus Controller (EBC):

The 82358DT EISA Bus Controller is part of Intel's 82350DT chip set. There are five mode or function select pins which allow the 82358DT to be programmed for use in either 82350 or 82350DT based systems. The mode pins also provide support for posted memory write cycles to the EISA/ISA bus and Intel486 burst support. The 82358DT defaults to 82350 mode and is 100% socket compatible with the 82358 (EBC).

The 82358DT interfaces the 386 and Intel486 microprocessors to the Extended Industry Standard Architecture (EISA) bus. It is used to facilitate bus cycles between the Host (CPU) bus and the EISA/ISA bus. In an 82350 system, the 82358DT interfaces to the cycle address and control signals of the Host bus. In an 82350DT system, the 82358DT interfaces to the cycle address and control signals of the 82359 DRAM controller. The 82358DT generates the appropriate data conversion and alignment control signals to implement an external byte assembly/disassembly mechanism for transferring data of different widths between the Host, EISA, and Industry Standard Architecture (ISA) buses. It also provides the cycle translation between the Host, EISA, and ISA buses.

The 82358DT is tightly coupled with the 82357 DMA controller (ISP) to run 8-. 16-, or 32-Sit EISA/ISA DMA transfers.

The 82358DT features hardware enforced I/O recovery logic to provide I/O recovery time between back-to-back I/O cycles.

The 82358DT provides special cache hardware interface signals to implement a high performance 386 based system with an 82385 or 82395 cache, controller.

The 82358DT also provides resets to the Inte1486, 80386, 82385, and other devices in the system to provide an integrated synchronous system reset.

Features:

• Supports 82350 and 82350DT Chip Set Based Systems
  • Mode Selectable for Either 82350 or 82350DT Based Systems
  • Mode Defaults to 82350 Based Cycles Systems
• Socket Compatible with the 82358 (EISA Bus Controller)
• Provides EISA/ISA Bus Cycle Compatibility
  • EISA/ISA Standard Memory or I/O Cycles
  • EISA/ISA Wait State Cycles
  • ISA No Wait State Cycles
  • EISA Burst Cycles
• Supports Intel386 & Intel486 Microprocessors
• Supports i486 Burst Cycles to the EISA/ISA Bus When Configured for 82350DT Systems
• Translates Host (CPU) and 82359 (DRAM Controller) Cycles to EISA/ISA Bus Cycles
• Generates ISA Signals for EISA Masters
• Generates EISA Signals for ISA Masters
• Supports 8-, 16-, or 32-bit DMA Cycles
  • Type A, B, or C(Burst) Cycles
  • Compatible Cycles
• Supports Host and EISA/ISA Refresh Cycles
• Generates Control Signals for Address and Data Buffers
  • 82353 (ADP) and 82352 (EBB)
• Supports Byte Assembly/Disassembly for 8-, 16-, or 32-Bit Transfers
• Selectable Host (CPU) Posted Memory Write Support to EISA/ISA Bus
• Cache Controller (82385, 82395) Interface to Maximize Performance for 386 Based Systems
• Supports I/O Recovery Mechanism
• Generates CPU, 82385, and System Software Resets
• 132-Pin PQFP Package
• Low Power CHMOS Technology