Description:

82356CS Memory to EISA Control (MECA)

This 160-pin device is responsible for the interface between the EISA bus and the Xpress Interface Bus. The control array component converts asynchronous memory cycles to synchronous cycles for the 82358DT EBC, and it arbitrates among the processor and bus masters for main memory control. This device initiates the Xpress bus snooping cycles and directly supports the write-through and write-back cache protocols. Memory decode and memory attributes are also integrated to support either parity or ECC memory modules.