Description:

Memory Controller (MC) Overview [82453KX (DC), 82452KX (DP), 82451KX (MIC)]

The combined MC (DC, DP, and four MICs) act as one physical load on the Pentium Pro processor bus. The DC provides control for the DRAM memory subsystem, the DP provides the data path, and the four MICs are used to interface the MC data path with the DRAM memory subsystem. The memory configuration can be either 2-way inter1eaved or non-inter1eaved. Both single-sided and double-sided SIMMs are supported. DRAM technologies up to 64 Mb at speeds of 50ns, 60ns, and 70ns can be used. Asymmetric DRAM is supported up to two bits of asymmetry (e.g., 12 row address lines and 10 columns address lines). The maximum memory size is 1 GB for the 2-way inter1eaved configuration and 512 Mbytes for the non-inter1eaved configuration using 16 Mbit technology. In addition to these memory configurations, the MC provides data integrity features including ECC in the memory array. These features, as well as a set of error reporting mechanisms, can be selected via configuration of the MC. Each inter1eave provides a 64-bit data path to main memory (72-bits including ECC).

The MC is PC compatible. All ISA and EISA regions are decoded and shadowed based on programmable configurations. Regions above 1 Mbyte with size 1 Mbyte or larger that are not mapped to memory may be reclaimed by setting the appropriate configuration in the MC. Three programmable memory gaps can be created and are called the Low Memory Gap Region, the Memory Gap Region and the High Memory Gap Region.

Features:

• Supports Pentium® Pro Processor 60 MHz and 66 MHz Bus Speeds
• Supports 64-Bit Data Bus and 36-Bit Address Bus
• Parity Protection on Control Signals
• Dual-Processor Support
• Eight Deep In-Order Queue
• Four Deep Outbound Request Queue
• Four Cache Line Read Buffer
• Four Cache Line Write Buffer
• GTL+ Bus Driver Technology
• Supports 3.3V and 5V SIMMs
• Read Access, Page Hit 8-1-1-1 (at 66 MHz, 60 ns DRAM)
• Read Access, Page Miss 11-1-1-1 (at 66 MHz, 60 ns DRAM)
• Read Access, Page Miss + Precharge 14-1-1-1 (at 66 MHz, 60 ns DRAM)
• 1 GB Maximum Main Memory
• 2-Way interleaved and non-Interleaved Memory Organizations
• Supports Standard 32 or 36-bit SIMMs
• Supports 72-bit DIMMs
• 4 Mbit, 16 Mbit and 64 Mbit DRAM
• Power Management of Memory Array
• Recovers DRAM Memory Behind Programmable Memory Gaps
• Available in 208-Pin QFP for the DC; 240-Pin QFP or 256-BGA for the DP; 144-Pin QFP for the MIC
• On-Chip Digital PLL
• JTAG Boundary Scan Support