Also known as:

• VLSI VL82C612 (DMA address register)

Description:

TI SN74LS612N Memory Mapper

Each 'LS612 memory mapper integrated circuit contains a 4-line to 16-line decoder, a 16-word by 12-bit RAM, 16 channels of 2-line to 1-line multiplexers, and other miscellaneous circuitry on a monolithic chip.

The memory mappers are designed to expand a microprocessor's memory addressing capability by eight bits. Four bits of the memory address bus can be used to select one of 16 map registers that contain 12 bits each. these 12 bits are presented to the system memory address bus through the map output buffers along with the unused memory address bits from the CPU. However, addressable memory space without reloading the map registers is the same as would be available with the memory mapper left out. The addressable memory space is increased only by periodically reloading the map registers from the data bus. This configuration lends itself to memory utilization of 16 pages of 2^(n-4) registers each without reloading (n - number of address bits available from CPU).

• Expands 4 Address Lies to 12 Address Lines
• Designed for Paged Memory Mapping
• Output Latches Provided on 'LS610
• 3-State Map Outputs
• Compatible with TMS9900 and Other Microprocessors