VLSI VL82C480 (System/Cache/ISA bus Controller)

Description:

Overview

The VL82C480 controller is designed to control 486DX or 486SX/487SX-based ISA bus systems operating at up to 40 MHz. It supports 64MB RAM. It replaces the following devices on the motherboard:

  • Two 82C37A DMA controllers
  • Two 82C59A interrupt controllers
  • 82C54 timer
  • 74LS612 memory mapper
  • 82284 clock generator and ready interface
  • 82288 bus controller

The following controller blocks are also included on-chip:

  • Memory/refresh controller
  • Port B and NMI logic
  • Bus steering logic
  • Turbo Mode control logic
  • Parity checking logic
  • Parity generation logic
  • Writ-back look-aside cache controller

In addition to the VL82C114 Combination I/O the additional configurations have been found:

  • VL82C480 + VL82C113A I/O
  • VL82C480 + 310 I/O support
  • VL82C480 + 312 I/O support
  • VL82C480 + 651 I/O support
  • VL82C480 + 721 I/O support
  • VL82C480 + SMC 661 I/O support

Differences to the VL82C481, see the VL82C481 for comparison between them.

Last updated 2019-04-30T00:00:00Z
drv No drivers available
doc No chipset documents available
chipdoc 2 chip documents available
Chip
Language
Release date
File
Last edit
Chip
Language
English
Release date
File
Last edit
pwr 2022-09-23
Chip
Language
English
Release date
File
Last edit
pwr 2022-09-27

Disclaimer

The info found in this page might not be entirely correct. Check out this guide to learn how you can improve it.