IBM PS/2 Model 80 T3 chipset

Chipset parts: Intel 82385 (32-bit Cache Controller for 80386) IBM 90X8134 (DMA) IBM 57X4111 IBM 23F3001 IBM 72X8299 (I/O controller) Intel 8259A-2 (Programmable Interrupt Controller) Motorola MC146818AP (Real-Time Clock + RAM) Intel 8042AH (Keyboard Controller)

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Release date:  1990-03-20      [see all boards with this chipset]


This is a radical departure from the Model 80 Type 1 & 2 motherboard. It was built around the Intel 385 Cache Controller. It includes two Intel 8259A-2.

Intel 82385 32-bit Cache Controller for 80386

Note: there are 3 versions released at different times: 82385 20 MHz Version 1987-02-16 82385 25 MHz Version 1988-04-04 82385 33 MHz Version 1989-04-01

The 82385 Cache Controller is a high performance 32-bit peripheral for Intel's 80386 Microprocessor. It stores a copy of frequently accessed code and data from main memory in a zero wait state local cache memory. The 82385 enables the 80386 to run at its full potential by reducing the average number of CPU wait states to nearly zero. The dual bus architecture of the 82385 allows other masters to access system resources while the 80386 operates locally out of its cache. In this situation, the 82385's "bus watching" mechanism preserves cache coherency by monitoring the system bus address lines at no cost to system or local throughput.

The 82385 is completely software transparent, protecting the integrity of system software. High performance and board savings are achieved because the 82385 integrates a cache directory and all cache management logic on one chip.

  • Improves 80386 System Performance
    • Reduces Average CPU Wait States to Nearly Zero
    • Zero Wait State Read Hit
    • Zero Wait State Posted Memory Writes
    • Allows Other Masters to Access the System Bus More Readily
  • Hit Rates up to 99%
  • Optimized as 80386 Companion
    • Simple 80386 Interface
    • Part of 386-Based Compute Engine Including 80387 Numerics Coprocessor and 82380 Integrated System Peripheral
    • 16 MHz, 20 MHz, and 25 MHz Operation
  • Software Transparent
  • Synchronous Dual Bus Architecture
    • Bus Watching Maintains Cache Coherency
  • Maps Full 80386 Address Space (4 Gigabytes)
  • Flexible Cache Mapping Policies
    • Direct Mapped or 2-Way Set Associative Cache Organization
    • Supports Non-Cacheable Memory Space
    • Unified Cache for Code and Data
  • Integrates Cache Directory and Cache Management Logic
  • High Speed CHMOS III Technology
  • 132-Pin PGA Package

90X8134 DMA

No datasheet exists for this chip. Sometimes labeled 90X8134ESD


This part is also labeled MS700CD on the model 80 type 3 motherboard. or MS700 on the P70 late motherboard. It is also found on the model 70 T1. T2 and T3. Conjecture: It is likely a gate array configured as perhaps a MCA interface. There has not been further investigation.


No datasheet exists for this chip. It is only found in the Model 80 Type 3 motherboard. Conjecture: this facilitates interface with the 385 cache controller.

72X8299 I/O controller:

No datasheet exists for this chip.

Intel 8259A-2 Programmable Interrupt Controller

mR_Slug notes:

Briefly the differences between the variants:

  • 8259A Data Valid From RD/INTA: Max 200ns c:79
  • 8259A-2 Data Valid From RD/INTA: Max 120ns c:81
  • 8259A-8 Data Valid From RD/INTA: Max 300ns c:79

It's quickest to replace like with like. Note the non-A version has many more differences to the A versions. For a summary of differences see the following link, or consult the datasheets.

mR_Slug Intel Chip Specifications 1975 - 1989

Intel 8259A-2 Programmable Interrupt Controller

The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology and requires a single +5V supply. Circuitry is static, requiring no clock input.

The 8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has several modes, permitting optimization for a variety of system requirements.

The 8259A is fully upward compatible with the Intel 8259. Software originally written for the 8259 will operate the 8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).

  • 8086, 8088 Compatible
  • MCS-80, MCS-85 Compatible
  • Eight-Level Priority Controller
  • Expandable to 64 Levels
  • Programmable Interrupt Modes
  • Individual Request Mask Capability
  • Single + 5V Supply (No Clocks)
  • 28-Pin Dual-In-Line Package
  • Available in EXPRESS
    • Standard Temperature Range
    • Extended Temperature Range

Motorola MC146818A Real-Time Clock + RAM:


  • MC146818P - plastic DIP
  • MC146818C - plastic DIP extended temp range.


  • MC146818A? - QFP (Datasheet states it is available, no p/n)
  • MC146818AC - plastic DIP extended temp range.
  • MC146818AL - ceramic DIP
  • MC146818AP - plastic DIP
  • MC146818AS - CERDIP
  • MC146818AF - SOP
  • MC146818AFN - PLCC

The A variant is newer. It has two additional pins, 1 and 16 that are NC on the non-A. Pin 1 is MOTEL, Tying it high or low determines if the chip uses Motorola or competitor e.g. Intel timing. Pin 16 is Standby. This was previously handled by the chip enable pin in the non-A. Details can be found on page 11 of both datasheets.

The MC146818A Real-Time Clock plus RAM is a peripheral device which includes the unique MOTEL concept for use with various microprocessors, microcomputers, and larger computers. This part combines three unique features: a complete time-of-day clock with alarm and one hundred year calendar, a programmable periodic interrupt and square-wave generator, and 50 bytes of low-power static RAM. The MC146818AFN uses high-speed CMOS technology to interface with 1MHz processor busses, while consuming very little power.

The Real-Time Clock plus RAM has two distinct uses. First, it is designed as a battery powered CMOS part (in an otherwise NMOS/TTL system) including all the common battery backed-up functions such as RAM, time, and calendar. Secondly, the MC146818A may be used with a CMOS microprocessor to relieve the software of the timekeeping workload and to extend the available RAM of an MPU such as the MC146805E2


  • Low-Power, High-Speed, High-Density CMOS
  • Internal Time Base and Oscillator
  • Counts Seconds, Minutes, and Hours of the Day
  • Counts Days of the Week, Date, Month, and Year
  • 3 V to 6 V Operation
  • Time Base Input Options: 4.194304 MHz, 1.048576 MHz, or 32,768 kHz
  • Time Base Oscillator for Parallel Resonant Crystals
  • 40 to 200 uW Typical Operating Power at Low Frequency Time Base
  • 4.0 to 20 mW Typical Operating Power at High Frequency Time Base
  • Binary or BCD Representation of Time, Calendar, and Alarm
  • 12- or 24-Hour Clock with AM and PM in 12-Hour Mode
  • Daylight Savings Time Option
  • Automatic End of Month Recognition
  • Automatic Leap Year Compensation
  • Microprocessor Bus Compatible
  • Selectable Between Motorola and Competitor Bus Timing
  • Multiplexed Bus for Pin Efficiency
  • Interfaced with Software as 64 RAM Locations
  • 14 Bytes of Clock and Control Registers
  • 50 Bytes of General Purpose RAM
  • Status Bit Indicates Data Integrity
  • Bus Compatible Interrupt Signals (IRQ)
  • Three Interrupts are Separately Software Maskable and Testable
    • Time-of-Day Alarm, Once-per-Second to Once-per-Day
    • Periodic Rates from 30.5 us to 500 ms
    • End-of-Clock Update Cycle
  • Programmable Square-Wave Output Signal
  • Clock Output May Be Used as Microprocessor Clock Input
    • At Time Base Frequency /1 or /4

Intel 8042AH Keyboard Controller:

mR_Slug notes:

This is the Intel UPI-42 (Universal Peripheral Interface 8042AH) programed as a keyboard controller and additional functions. It was released around '87. The 8042AH is a ROM mask (programmed at the factory). It is pin compatible with the 8042 and EPROM based 8742AH.

An 8042AH will NOT function as a keyboard controller UNLESS it is programed to do so. Programs can differ between 8042AH's. In this application, for FULL OPERATION in a motherboard the program MUST be correct. Typically, swapping an 8042AH from a PC to another, will often provide a functional keyboard, the additional functions may not work. It may be labeled as 'Keyboard BIOS'. Using an 8042AH programmed for some other (non-PC) application will NOT work.

Intel 8042AH Universal Peripheral Interface:

The Intel UPI-42 is a general-purpose Universal Peripheral Interfaces that allow the designer to develop customized solutions for peripheral device control.

They are essentially "slave" microcontrollers, or microcontrollers with a slave interface included on the chip. Interface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS Modules and iAPX family, as well as other 8-, 16-bit systems.

To allow full user flexibility, the program memory is available in ROM, One-Time Programmable EPROM (OTP) and UV-erasable EPROM. All UPI-42 devices are fully pin compatible for easy transition from prototype to production level designs, These are the memory configurations available.

UPI Device ROM EPROM RAM Programming Voltage 8042AH 2K - 256 - 8742AH - 2K 256 12.5V

  • UPI-42: 12 MHz
  • Pin, Software and Architecturally Compatible with all UPI-41 and UPI-42 Products
  • 8-Bit CPU plus ROM/EPROM, RAM, I/O, Timer/Counter and Clock in a Single Package
  • 2048 x 8 ROM/EPROM, 256 x 8 RAM on UPI-42, 8-Bit Timer/Counter, 18 Programmable I/O Pins
  • One 8-Bit Status and Two Data Registers for Asynchronous Siave-to-Master Interface
  • DMA, Interrupt, or Polled Operation Supported
  • Fully Compatible with all Intel and Most Other Microprocessor Families
  • Interchangeable ROM and EPROM Versions
  • Expandable I/O
  • Sync Mode Available
  • Over 90 Instructions: 70% Single Byte
  • Available in EXPRESS
    • Standard Temperature Range
  • Intelligent Programming Algorithm
    • Fast EPROM Programming
  • Available in 40-Lead CERDIP, 40-Lead Plastic and 44-Lead Plastic Leaded Chip Carrier Packages
Drivers: not available
Documentation: 1 file
Other files: not available