Overview

This entry is for the non cached version without the VL82C335 cache controller. For the cached version see here. The VL82C106 part is optional.

The TOPCAT 386DX chip set from VLSI Technology, Inc., is a very high integration chip set for use in the design of PC/AT-compatible based systems. This chip set is intended for use in 80386DX microprocessor-based systems with clock speeds form 16 to 33 MHz.

The TOPCAT 386DX chip set provides design engineers with a very flexible, high- performance, low-cost board design solution for IBM PC/AT-compatible desktop, laptop, portable, and hand-held computers.

The TOPCAT 386DX three-device chip set has been designed with the highest integration consistent with economic and reliable system design. It provides a complete board design using only 10 non-memory devices including the microprocessor.

VLSI's The TOPCAT 386DX chip set was designed with seven goals.

lowest system board cost
Smallest board area requirement
highest performance in both cached and non-cached systems
single board design for:
- 16 to 33 MHz operation
- Cache or non-cache
- 1M byte to 64M byte memory using 256K, 1M, and 4M bit DRAM
- Laptop or desktop applications
Full hardware LIM EMS 4.0 support for the highest possible performance
Built-in, in-circuit test modes for easy board level testing.
the VL82C330A interfaces to the VL82C335 "look-aside" Cache Controller

Features

Three chip, PC/AT-compatible chip set capable of use in 80386DX-based systems from 16 to 33 MHz
Two 128-lead and one 160-lead plastic quad flatpacks, 1.0 and 1.5 micron CMOS
Memory control of one to four banks of 32-bit DRAM using 256K. 1M or 4M components allowing 64M bytes on system board
Two-/four-way page mode interleaving or direct access on system board memory
Programmable DRAM timing parameters
Remap option allows logical reordering of system board DRAM banks
Staggered system board refresh optionally decoupled from slot bus refresh
Built-in "sleep" mode features, including use of slow refresh DRAMs in power critical operations
Hardware supports full EMS 4.0 spec over entire 64M byte memory map
DMA expanded to allow transfers over 64M byte range
Shadow RAM support in 16K increments
Support for 80387DC and Weitek 3167 numerical coprocessors
Internal switching and programmable CPU clock support for PC/AT-compatible and "turbo" modes
Asynchronous or synchronous slot bus with "Bus Quiet" mode
Built-in real-time clock and scratchpad RAM
Additional 64 bytes of battery backed RAM in RTC
Supports 8- or 16-bit wide BIOS ROMs
Cache support for posted writes
In-circuit test modes
Support for the VL82C335 Cache Controller is provided by the VL82C330A